Risk Modeling Manager jobs in Goodyear, AZ

Job Description

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's IDM2.0 strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in high-volume manufacturing at a 2-year cadence going forward. Intel recently created HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.
This job requisition is to seek Yield Modelling manager in FSM HVM Global Yield organization, reporting to Director of Yield Analysis and Data Science (YA and DS). The selected candidate will build and lead a team in HVM Global Yield organization and work with other leaders in the org, fab module/yield managers and TD leaders to support yield ramp-up and process optimization in early production stage, supporting internal and external customers.
Yield Modeling Manager responsibilities include (but not limited to):
- Build and lead Yield Modeling team with machine learning and modeling experts in FSM HVM Global Yield organization to define and drive HVM yield roadmap.
- Develop a model to predict production line yield accurately in early stage of Si progression and deliver proposals to benefit production yield.
- Develop new yield modelling methods and algorithms to deliver world class yield predictability and machine-learning solutions in high-volume manufacturing environment.
- Collaborate with Data Science team to incorporate large-volume yield, defect, parametric and manufacturing data into yield modelling.
- Track inline process and non-process changes to incorporate the changepoints into yield prediction model.
- Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device and Module teams to develop projects to eliminate systematic yield losses.
- Collaborate with Program Managers, Process Integration, Device Integration and Defect team managers to identify novel yield enhancement approaches and opportunities in high-volume manufacturing environment.
- Lead technical interactions with internal and external customers.
Candidate should possess the following behavioral skills:
- Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
- Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
- Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
- Must demonstrate strong communication skills.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Bachelor's degree in science or engineering area.
5 years of experience in advanced node semiconductor industry in data science and analysis/modelling.
3 years of leadership experience to manage and direct an organization of 5 data analysis engineers in fast-paced high-volume semiconductor manufacturing environment to drive yield, technology, quality output and cost.
3 years of experience to project DOI (Defect of Interest) kill ratio.
3 years of experience in setting up yield projection modeling based on product yield and product layouts
3 years' experience in python and other program languages to develop a new analysis method and algorithms using large amount of fab data. Expertise in big data analysis and machine-learning.
2 years' experience in Device Physics and overall FinFET process flow.

Preferred Qualifications:
Ph.D. or Master's in science or engineering area.
Experience in serving external Foundry customers through technical interactions.
Experience in new semiconductor technology development
Basic understanding on module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

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